FPGA Implementation of the Pipelined Data Encryption Standard (DES) Based on Variable Time Data Permutation

This paper describes a high-performance reconfigurable hardware implementation of the new Data Encryption Standard (DES) based on variable time data permutation. The permutation choice is variable with time. For the same data and key, the ciphered data is varied with time, so the security of the algorithm is increased. We have used the pipelining concept in our design. Our DES is implemented on Xilinx Spartan-3e (XC3s500e). Final 16-stage pipelined design is achieved with data rate of 7.98 Gbps and 2062 CLB slices. The proposed design is more secure and among the fastest hardware implementations with better area utilization. KeywordsData Encryption Standard (DES) Algorithm, Field Programmable Gate Arrays (FPGA), Pipelining, Variable Time Data Permutation.